Universal carrier tray

ABSTRACT

A carrier tray is provided for holding a semiconductor device that has a two dimensional array of regularly spaced rows and columns of holes having one and only one pitch and one and only one pocket size. The holes are configured to receive a solder ball from a ball grid array package. The carrier tray can engage at least two differently sized ball grid array packages, thereby avoiding the expense and long lag time associated with designing a new product carrier tray for each new semiconductor device.

TECHNICAL FIELD

The present invention relates to the field of semiconductor manufacture,and more specifically to a universal carrier tray for holding integratedcircuit devices.

BACKGROUND ART

The Plastic Ball Grid Array (PBGA) package is a relatively new packagedesign which is gaining popularity as an attractive package solution formemory and microprocessor devices. It offers a high-density package witha smaller form/fit factor than a comparable leadcount quad flat packpackage. More importantly, it is designed with solder balls instead ofleads, and they are more durable and loosely pitched than the fragilepackage leads of a comparable surface-mount component. This results inhigher board yields.

The PBGA package consists of a thin Printed Circuit Board (PCB) made ofa BT epoxy laminate, double-sided, and overlaid with copper over whichmetallized wire bond pads and a die pad are fabricated. The wirebondpads extend outward to plated through-hole-vias located around theboard's periphery. These vias provide the electrical continuity from thetop of the board to the other side where copper traces run from theholes to a matrix of solder bumps. The bumps are soldered onto a landpattern on a circuit board in the end-use application. A solder mask isphoto defined on the backside of the package to contain the flow ofsolder during board assembly.

The die is attached to the die pad using a standard epoxy die attachmethod. Gold ball bonding is used to connect the die pads to the wirebond pads, and the die of overmolded with silicone-modified, epoxynovolac encapsulation material to protect it.

The PBGA package design offers many advantages over other high leadcountpackages. Because of the small package size, the BGA offers significantsavings in board real estate, occupying about 51% of the space acomparable quad flat pack (QFP) requires. It has a lower profile, too,about one third as thick as a plastic quad flat pack (PQFP) package.

The BGA offers superior electrical performance because the shorterwirebond lengths in it help reduce inductance. Comparing a 169-ball BGAto a 160-ball PQFP, the BGA shows a 31 percent reduction in signalcapacitance and a 46 percent reduction in signal time delay.

Studies have been conducted that show the BGA to thermally outshine acomparable PQFP when it is fabricated with “thermal vias” (i.e.,through-hole vias) underneath the die pad. These vias allow heatgenerated by the device to flow to the board, which would improvethermal performance provided the board has a conducting plane built intoit. However, thermal data shows that a thermal performance of the BGA(without thermal vias) is not as good as a comparable PQFP. Whencomparing a BGA with thermal vias to a PQFP with a heat sink attached tothe lead frame, the BGA still does not perform as well. To moreaccurately ascertain the performance of a BGA, the specific end-useapplication environment needs to be considered.

The pitch of the solder balls on a BGA is far more manageable duringboard assembly, at 1.0 to 1.5 mm, than the typical of 0.5-mm pitch ofhigh lead count Quad Flat Packs (QFPs).

BGAs can be handled with the same pick-and-place equipment that is usedfor conventional surface-mount devices, including solder reflow methods.During reflow assembly, the wetting action of the solder balls tends topull them into alignment so that placement of the component on thesolder land does not need to be nearly as precise as with a QFP. Thealignment can be off by as much as 6 mils—more forgiving than the 3 mils(0.076 mm) required for fine lead-pitch QFPs.

New BGA packages are constantly being developed having varying bodysizes, number of solder balls, and package design including cavity-up orcavity-down configurations, as well as interconnections formed usingwirebonding or flip-chip technology. Typically, as each new BGA packageis designed, a corresponding tray with holes configured to receive thesolder balls on the BGA must be produced. This process is bothtime-consuming and costly.

There exists a need for an effective product carrier tray for asemiconductor device which eliminates problems associated with therequirement for a new product carrier tray for each new product.

There is also a need for an effective product carrier that eliminatesthe expense and long lag time associated with designing a new productcarrier tray for each new semiconductor device.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a carrier tray is provided forholding a semiconductor device. The carrier tray includes a twodimensional array of regularly spaced rows and columns of holes havingone and only one pitch and having one and only one pocket size. Theholes are configured to receive a solder ball of a ball grid arraypackage.

Another aspect of the present invention is a method for manufacturingsuch a semiconductor carrier. The method includes the step of moldingplastic into the desired configuration.

A further aspect of the present invention is an assembly that includes acarrier tray for holding a semiconductor device. The carrier trayincludes: a two dimensional array of regularly spaced rows and columnsof holes having one and only one pitch and one and only one pocket size,and the holes are configured to receive a solder ball of a ball gridarray package. The assembly further includes at least two differentlysized ball grid array packages comprising solder balls engaged in theholes of the carrier tray.

Other advantages of the present invention will become readily apparentto those skilled in this art from the following detailed description.The embodiments shown and described provide illustration of the bestmode contemplated for carrying out the invention. The invention iscapable of modifications in various obvious respects, all withoutdeparting from the invention. Accordingly, the drawings are to beregarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is made to the attached drawings, wherein elements having thesame reference numeral designations represent like elements throughout.

FIG. 1 illustrates a cross-section of a plastic ball grid array package;

FIGS. 2A-2B illustrate a bottom view of two different BGA packages; and

FIGS. 3A-3B illustrate an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a cross-section of a plastic ball grid array package100. The elements of the plastic ball grid array include solder balls102, copper foil pads and interconnects 104, plated copper conductor 106and die pad 108. The package further comprises die attach epoxy 110, die112, epoxy glob top 114, and bonding wire 116. Additional elements ofthe package include plated through hole 118, solder mask 120, BT epoxycircuit board 122 and thermal ground vias 124.

Adverting to FIGS. 2A-2B, FIG. 2A illustrates a bottom view of a BGApackage 200. Package 200 includes solder balls 202. FIG. 2B illustratesa bottom view of a BGA package 250 including solder balls 252. It shouldbe appreciated that the overall thickness of each package as well asdimensions including ball height body thickness, seating plane clearancebody size, ball footprint, ball matrix size, total ball count, ballpitch and number of rows and columns deep may all differ from onepackage to another. As a result, each new package requires a new carriertray configured for the particular package.

With reference to FIG. 3A, illustrated is a top view of carrier tray300, for holding a semiconductor device 310. FIG. 3B illustrates a sideview of carrier tray 300. Carrier tray 300 includes a two dimensionalarray of regularly spaced rows and columns of holes 315. The regularlyspaced rows and columns of holes have one and only one pitch. Moreover,the two dimensional array of regularly spaced rows and columns of holeshave one and only one pocket size. Holes 315 are configured to receive asolder ball of a ball grid array package. In various embodiments, thecarrier tray can be configured to hold a cavity-down package or can beconfigured to hold a cavity-up package. Also, in embodiments of thepresent invention, the carrier tray includes holes configured toaccommodate solder balls having a height from about 0.50 mm to about0.70 mm.

In embodiments of the present invention, the carrier tray can beconfigured to accommodate solder balls 320 having a diameter from about0.60 mm to about 0.90 mm. Also, the holes can be configured toaccommodate solder balls having a pitch from about 1.25 mm to about 1.29mm.

Furthermore, in embodiments of the present invention, the carrier traycan be configured to accommodate one or more packages 310, 311, 312having a ball count of at least 256. In addition, the carrier tray canbe configured to accommodate one or more packages having a ball countfrom about 256 to about 492. An aspect of the present invention,however, is that the carrier tray can accommodate packages of varyingsizes, e.g, 2 or more, such as 4-8, so long as the solder balls have oneand only one pitch as well as one and only one pocket size. Ideally, alldevices are uniformly oriented so pin one is aligned with the notchedcorner 320 of the tray 300.

The carrier tray is formed from a material, e.g., plastic. It will beappreciated that other materials suitable for forming relatively thin,sturdy structures can be used to form the tray. Exemplary materialsinclude, for example, conductive thermoplastic, non-conductive andinsulated plastic, antistatically coated PVC, antistatically coatedpolysulfone (to provide protection from ESD damage and to eliminate thepotential for low leakage between component leads), conductivecarbon-filled polypropylene, and black dissipative BPI-10 plastic. Incertain embodiments, the carrier material can withstand temperatures upto about 40° C. to about 60°, for example, temperatures of 125° C. to150° C. The material can also include a carbon-based material or beantistatically coated to provide ESD protection.

Multiple trays of product can be stacked for shipment with an additionaltray serving as a cover. All devices can be uniformly oriented so pinone is aligned with the notched corner 320 of tray 300.

The product carrier of the present invention may comprise one or morematerials and/or may comprise one or more layers of material. Further,the inventive product carriers may comprise a recycled material, such asabout 5% to 30% recycled materials

In the embodiment illustrated in FIG. 3B, the tray is configured toaccommodate multiple semiconductor devices. However, the inventiveproduct carrier may be configured to accommodate a single device and/orproduct carriers may be configured to accommodate a plurality ofdevices, one or more devices each of which is already being held in anindividual carrier as well as different devices with differingconfigurations.

The inventive product carriers are uniformly sized, in compliance withstandard JEDEC outlines. The inventive product carriers are also sizedto ensure that there is no excessive movement of product during shippingand handling. This protects the mechanical integrity of the packageincluding the solder balls; it also ensures an unimpaired dispensing ofproduct for manufacturing operations.

For shipment, a stack of trays, for example, six trays, can be securedwith straps; five containing parts and the sixth serving as a cover.Bound trays may then be loaded into an antistatic bubble pack bag, forextra cushioning protection, and then packed in a tray box for shipment.Included in the dry pack bag are a prescribed number of humidityindicator cards and desiccant pouches, depending on the quantity ofdevices in the bag.

The inventive product carrier can be made by molding a material, such asmolten plastic, into the desired shape, as with conventional techniques.

Upon determination that a product is moisture sensitive , the product isdry packed for storage and shipment. The first step in the dry packprocess is to remove any moisture buildup in the package by baking thefinished product for 5 to 15.5 hours, depending on the package type, at125° C. +/−5° C. While baking, the product is contained in the productcarriers (provided the carrier is made of material that can withstandthe high temperature) or aluminum trays or tubes. Within 50 hours afterbaking, the product is sealed in a dry pack bag under a partial vacuum.

An exemplary dry pack bag (i.e., moisture barrier bag) is designed withthree layers. The inner layer is a low-density polyethylene, which has astatic-dissipative coating. A second layer is 400 angstroms aluminummetallized to 92-guage polyester. The third layer is 400 angstromaluminum metallized to 92-guage polyester, which has astatic-dissipative coating. ESD protection is provided by the innerlayer of antistatic polyethylene and the second layer of aluminummetallized polyester.

The bag is sealed using an impulse heat sealer at a seal time of about1.0 to about 1.5 seconds; and a seal pressure of about 40 to about 50psi; and a temperature range of about 191 to about 232° C.

Included in each dry pack bag is a card that has humidity sensitiveelements which turn from blue to pink whenever the specific RH level isexceeded.

Labels may also be applied to the outside of the dry pack bag. Forexample, a standard product label, which identifies the contents bymanufacturing lot number, product part number, and the product datecode(s) and quantity per date code. Also, a dry pack caution label,which identifies the date the bag was sealed, the dry pack expirationdate (which is 12 months later)), as well as product handlingguidelines. A small moisture-sensitivity caution label may also beapplied to the outside of the box in which the dry packed parts arepacked.

Described has been a carrier and method for manufacturing an apparatusthat is a carrier for semiconductor devices. An advantage of theinvention is that it can easily be implemented and is both efficient andcost-effective. Another advantage of the invention is that it is readilyfabricated and customized to various semiconductor devices. In thisdisclosure, there is shown and described only certain preferredembodiments of the invention, but, as aforementioned, it is to beunderstood that the invention is capable of use in various othercombinations and environments and is capable of changes or modificationswithin the scope of the inventive concept as expressed herein.

What is claimed is:
 1. An assembly comprising: a carrier tray forholding a semiconductor device, the carrier tray comprising: a twodimensional array of regularly spaced rows and columns of holes havingone and only one pitch and one and only one pocket size, said holesbeing configured to receive a solder ball of a ball grid array package;and at least two differently sized ball grid array packages comprisingsolder balls engaged in the holes of the carrier tray.
 2. The assemblyof claim 1, wherein the carrier tray is configured to hold a cavity-downpackage.
 3. The assembly of claim 1, wherein the carrier tray isconfigured to hold a cavity-up package.
 4. The assembly of claim 1,wherein the carrier tray comprises holes configured to accommodate ballshaving a height from about 0.50 mm to about 0.70 mm.
 5. The assembly ofclaim 1, wherein the carrier tray comprises holes configured toaccommodate balls having a diameter from about 0.60 mm to about 0.90 mm.6. The assembly of claim 1, wherein the carrier tray comprises holesconfigured to accommodate balls having a pitch from about 1.25 mm toabout 1.29 mm.
 7. The assembly of claim 1, wherein the carrier traycomprises holes configured to accommodate a package having a ball countof at least
 256. 8. The assembly of claim 1, wherein the carrier traycomprises holes configured to accommodate a package having a ball countfrom 256 to
 492. 9. The assembly of claim 1, wherein the carrier tray ismade of 25% recycled material.
 10. The assembly of claim 1, wherein thecarrier tray comprises polyvinyl chloride and is either carbon-filled orantistatically coated to provide ESD protection.
 11. The assembly ofclaim 3, wherein the carrier tray material comprises about 5% to about30% recycled materials.
 12. The assembly of claim 3, wherein the carriertray further comprises a notched edge.
 13. The assembly of claim 3,wherein the carrier tray is made by molding.